A content addressable memory (CAM) device is a storage device having an array of memory cells that can be instructed to compare the specific pattern of comparand data with data words stored in corresponding rows of the array. The entire CAM array, or segments thereof, are searched in parallel for a match with the comparand data. If a match exists, the CAM device indicates the match condition by asserting a match flag, and may indicate the existence of multiple matches by asserting a multiple match flag. The CAM device typically includes a priority encoder that provides the highest priority matching address (e.g., the lowest matching CAM index) to a status register. The highest priority matching address, the contents of the matched location, and other status information (e.g., skip bit, empty bit, full flag, as well as match and multiple match flags) may be output from the CAM device to an output bus. In addition, associative data may be read out from an associated addressable storage device (e.g., DRAM).
Due to the rapidly increasing number of addressable sites on the Internet, there is an ongoing desire to increase the storage capacity of CAM devices used for Internet routing applications. This ongoing desire fuels development of future generations of CAM devices that have more storage capacity than previous generations. Each new generation of CAM devices typically has about twice the storage density as previous generation CAM devices.
The ability to be the first to market in offering a next generation CAM device having twice the storage capacity of current generation CAM devices provides a distinct competitive advantage. However, implementing a CAM device in a new process technology to double the storage density requires considerable time and expense, and may be dependent upon others (e.g., wafer manufacturers) to perfect the new process technology. Alternately, creating a new array architecture having twice the storage capacity using current process technology may require considerable time and expense to develop, and may occupy as much as twice the area of the silicon wafer. As a result, the number of manufacturing defects on the wafer that affect the CAM array increases, thereby decreasing manufacturing yield. Further, the increased size of the CAM array may result in the CAM die exceeding present photolithographic stepping dimensions, e.g., the photolithographic stepping fields may be smaller than the individual dice, in which case fabrication using present process technology may not be possible.
Thus, it is desirable to increase the storage capacity of CAM devices without having to develop a new process technology or CAM array architecture.